Integrated circuit (IC) devices typically include an IC chip which is housed in a plastic or ceramic "package". The IC chip is typically a piece of a thin wafer of silicon upon which an integrated circuit is formed. The package supports and protects the IC chip and provides electrical connections between the integrated circuit and an external circuit or system.
There are several package types, including ball grid arrays, pin grid array (PGAs), plastic leaded chip carriers, and plastic quad flat packs. Each of the package types is typically available in numerous sizes. The package type selected by an IC device manufacturer for a particular IC chip is typically determined by the size/complexity of the IC chip (i.e., the number of input/output terminals), and also in accordance with a customer's requirements.
FIG. 1 shows a side view of an IC device 100 including an IC chip 110 mounted in a typical PGA package 120. IC chip 110 is mounted in a cavity formed in a lower surface 122 of package 120. Package 120 includes a plurality (four shown) of pins 124 which extend from lower surface 122 of the package body and are electrically connected to IC chip 110 using conductive lines (not shown). Pins 124 have a fixed length L which is measured from bottom surface 122. In addition, two or more of the pins 124 typically include a widened annular ("stand-off") portion 126 which maintains lower surface 122 at a fixed standoff distance S from a host PCB. A distance from a lower surface 112 of IC chip 110 to the tips of pins 124 is known as a projection distance P.
As with most package types, PGA packages are provided with a multitude of different package sizes, numbers of pins and pin arrangements (hereafter referred to as "footprints"). FIGS. 2(A) through 2(K) show the footprints of several PGA packages illustrating some of these variations. FIG. 2(A) shows a PG299 package which includes 299 pins formed in rows (1-20) and columns (A-X) around a central cavity which is provided for an IC chip. Likewise, FIGS. 2(B) through 2(J) show the footprints for PG223, PG191, PG175, PG156, PG144, PG132, PG120, PG84 and PG68 packages, respectively. Finally, FIG. 2(K) shows a high density PG447 package having 447 pins. FIGS. 2(A) through 2(K) illustrate footprints representing a set of PGA packages used by a single IC manufacturer to house its IC chips. In addition to the differences in footprints, the IC manufacturer must also provide different pin lengths L, standoff distances S and projection distances P of the pins associated with the various PGA packages, as discussed above with respect to FIG. 1.
IC device testing systems are used by IC manufacturers to test their IC devices before shipping to customers. IC device testing systems typically include a device tester, a device handler and an interface structure. A device tester is an expensive piece of computing equipment which transmits test signals via tester probes to the leads of an IC device, and processes signals received from the IC device. A device handler is an expensive precise robot for automatically moving IC devices from a storage area to the tester probes and back to the storage area. The interface structure is connected to the tester probes, and includes a test area (i.e., socket arrangement) for receiving IC devices from the device handler. When an IC device is mounted in the test area, electrical connections are made from the IC device through the sockets of the interface structure to the tester probes of the tester.
Device testers and device handlers are typically purchased by IC manufacturers from different companies. The choice of a particular device tester depends in part upon the number of pins associated with the IC manufacturer's IC devices. That is, the device tester must have a number of tester probes which is equal to or greater than the number of pins utilized by an IC device. Similarly, device handlers are selected based on, for example, the required throughput (i.e., the rate at which IC devices are to be tested).
Interface structures are often custom made for or produced by an IC device manufacturer to interface between a particular device tester and a particular IC device produced by the manufacturer. Each interface structure must be built to contact the tester probes of the device tester, and to provide a test area having an arrangement of contacts which matches the footprint of the IC device to be tested.
FIG. 3 shows a top view of an interface structure 300 described by the present inventor in commonly-assigned patent application 08/541,567 Docket X-160! which is used to test IC devices housed in PGA packages. Interface structure 300 includes vias 310 arranged in groups which are spaced around the perimeter of a disk-shaped printed circuit board (PCB) 320 and extend toward the center of PCB 320. The arrangement of vias 310 shown in FIG. 3 represents that which must be used with the SC212 tester from Credence Systems Corporation. Vias 310 are mounted onto and receive male tester probes extending from the device tester (not shown). Several (48) vias 310 are connected by metal traces 330 to sockets 340 of a centrally-located test area 350. An IC device 360 (indicated by dashed lines) is mounted in the test area 350 such that the pin terminals (not shown) which extend from the PGA package of the IC device 360 are received in the sockets 340. After IC device 360 is mounted, the test device transmits test signals through the male tester probes (not shown) to the vias 310, and along traces 330 to the pin terminals of IC device 360. Similarly, return signals from IC device 360 are transmitted to the test device through sockets 340, traces 330 and vias 310.
A problem with the interface structure 300 is that it makes inefficient use of the device tester (not shown) to which the interface structure 300 is mounted because the space provided for the test area 350 is too small to handle multiple IC devices. Assume that an IC manufacturer has two IC devices having 96 pins and 48 pins, respectively. The IC manufacturer must purchase a tester having 96 tester probes to test the IC device having 96 pins, and may also use the tester to test the IC device having 48 pins. Interface structure 300 may be used to test the 48-pin IC device. However, during each test iteration of the 48-pin IC device, many of the tester probes of the tester are not in use, thereby making inefficient use of the tester.
FIG. 4 shows an exploded perspective view of a second interface structure 400 which includes a disk-shaped mother board 410, a disk-shaped daughter board 420 and a contactor 430. The second interface structure is designed to overcome the limitations of the interface structure 300 (see FIG. 3) by expanding the test area, thereby permitting a tester to test multiple IC devices at the same time, while minimizing any signal loss, and without necessitating any change in the spacing and location of the groups of tester probes in order to be compatible with standard automatic test equipment (ATE) testers.
FIG. 5 shows the top surface of mother board 410. Similar to the interface structure 300 (FIG. 3), mother board 410 includes vias 510 which are formed into groups and which extend to the bottom surface of board 410 and make contact with correspondingly placed male probes of a tester. The configuration of vias 510 shown in FIG. 5 represents the arrangement which must be used with the SC212 tester from Credence Systems Corporation. Compressible probes ("pogo pins") 512 are arranged in groups between adjacent groups of vias 510 and extend upward from the top surface of mother board 410. The pogo pins 512 are connected through metallization (not shown) to corresponding vias 510. Reinforced apertures 513 are provided around the perimeter of mother board 410, and adjacent to pogo pin groups 512 for receiving a shoulder bolt connected through the daughter board 420 (as discussed below). Guide pins 514 are positioned asymmetrically in mother board 410 and extend upward from mother board 410.
FIG. 6 shows a top surface of daughter board 420 which can be used with mother board 410. Daughter board 420 includes contact pads (contacts) 622 arranged in groups for contacting corresponding pogo pins 512 on mother board 410. Reinforced apertures 623 receive the shoulder bolts which connect daughter board 420 to mother board 410. When the shoulder bolts are tightened, contacts 622 press against pogo pins 512. Guide apertures 624 receive guide pins 514 from mother board 410 and assure proper alignment of all pogo pins to corresponding contacts. Three groups 625 of pogo pin receptacles 628 are arranged in the central portion of daughter board 420. Metallization lines 627 illustrate connections between contacts 622 and pogo pin receptacles 628.
FIG. 7 shows a cross section side view of a portion of contactor 430 mounted on daughter board 420. Contactor 430 includes a vespel purge plate 731 (vespel is an extremely hard, non-conductive, anti-static plastic having a thermal expansion coefficient similar to aluminum and able to tolerate a wide temperature range) which rests on the upper surface of the daughter board 420, a metal contactor base 732 mounted on the purge plate 731, and a metal contactor body 733 mounted on the contactor base 732. The contactor body 733 incorporates a plurality of dual spring-probe pogo pins 734, each pogo pin 734 having an upper tip 735 exposed through an upper surface 736 of contactor body 733, and a lower tip 737 extending through the contactor base 732 and vespel purge plate 731 to contact a pogo pin receptacle 628 on daughter board 420. When a handler device mounts an IC device 100 onto the contactor 430, each pin 124 of IC device 100 contacts the upper tip 735 of one of the pogo pins 734. Test signals are thereby transmitted to and from the IC device 100 through the pogo pins 734 to the pogo pin receptacles 628, along the metallization lines 627 to the contacts 622 (FIG. 6), through the pogo pins 512 to the vias 510 (FIG. 5), and from the vias 510 to the tester probes of the tester (not shown).
The interface structure 400 is a significant improvement over the interface structure 300 in that it provides an expanded work area which allows simultaneous testing of two or more IC devices, thereby making more efficient use of a device tester.
Although interface structure 400 is a significant improvement over interface structure 300, several problems have arisen regarding interface structure 400.
First, electrical contacts between contactor 430 and daughter board 420 are often damaged or contaminated, thereby introducing production delays or undesirable resistances which produce erroneous test results. The purpose for contactor 430 is to protect both the IC device being tested and daughter board 420 during mounting by a device handler. For this reason, contactors 430 are designed as expendable parts which are subject to damage when, for example, a handler improperly presses an IC device against a contactor 430 with excessive force. When this occurs, the pogo pins 734 can be damaged, thereby requiring expensive interruptions in the testing process. Further, prolonged use of the contactors typically results in tin-lead contamination at the contact points between at the IC devices and the upper tips 735 of the pogo pins 734, and between the lower tips 737 of pogo pins 734 and the pogo pin receptacles 628 of daughter board 420, thereby introducing resistances which generate erroneous test results.
Second, although one mother board 410 may be produced for each device tester, each IC device requires a separate daughter board 420 and contactor 430. That is, although mother board 410 is universal to all IC devices tested on a particular device tester, daughter boards 420 and contactors 430 are produced specifically for each IC device. This requires an IC manufacturer to purchase or produce at least one daughter board 420 and contactor 430, which cost thousands of dollars each, for each type of IC device produced by the manufacturer. This limits the IC manufacturer's ability to stock replacement daughter boards and contactors, thereby causing production delays when the daughter board and/or contactor for a particular IC device fails during testing.